“RDMA and collective throughput recover with lower cross-socket traffic” addresses nIC and GPU placement creates avoidable cross-socket transfers, but the current hardware or infrastructure issue is host power-management policy is starving the application input pipeline. The option “steady GPU occupancy increases as preprocessing throughput recovers” is more directly tied to the required outcome.

“input wait time declines and accepted training throughput rises” addresses storage I/O and host page cache behavior constrain accelerator feeding, but the current hardware or infrastructure issue is host power-management policy is starving the application input pipeline. The option “steady GPU occupancy increases as preprocessing throughput recovers” is more directly tied to the required outcome.

“chosen policy meets throughput and p99 latency targets reproducibly” addresses cPU scheduling configuration was assumed to be universally beneficial, but the current hardware or infrastructure issue is host power-management policy is starving the application input pipeline. The option “steady GPU occupancy increases as preprocessing throughput recovers” is more directly tied to the required outcome.

Useful for host software concurrency exceeds useful CPU processing capacity, but it does not remove the specific condition: NIC and GPU placement creates avoidable cross-socket transfers.

“align qualified BIOS processor and software profiles before comparing HPL” addresses platform tuning baselines are inconsistent across seemingly identical servers, but the current hardware or infrastructure issue is nIC and GPU placement creates avoidable cross-socket transfers. The option “choose qualified PCIe and NUMA-local NIC-to-GPU affinity” is more directly tied to the required outcome.

“bind data-loader processes and memory to the GPU-local NUMA domain” addresses nUMA memory locality increases transfer latency and CPU-to-GPU traffic, but the current hardware or infrastructure issue is nIC and GPU placement creates avoidable cross-socket transfers. The option “choose qualified PCIe and NUMA-local NIC-to-GPU affinity” is more directly tied to the required outcome.

“input wait time declines and accepted training throughput rises” addresses storage I/O and host page cache behavior constrain accelerator feeding, but the current hardware or infrastructure issue is nIC and GPU placement creates avoidable cross-socket transfers. The option “RDMA and collective throughput recover with lower cross-socket traffic” is more directly tied to the required outcome.

“packet receive rate improves and no single core saturates at peak traffic” addresses interrupt handling placement bottlenecks ingress traffic, but the current hardware or infrastructure issue is nIC and GPU placement creates avoidable cross-socket transfers. The option “RDMA and collective throughput recover with lower cross-socket traffic” is more directly tied to the required outcome.

“profiler shows lower remote memory access and improved batch delivery” addresses nUMA memory locality increases transfer latency and CPU-to-GPU traffic, but the current hardware or infrastructure issue is nIC and GPU placement creates avoidable cross-socket transfers. The option “RDMA and collective throughput recover with lower cross-socket traffic” is more directly tied to the required outcome.

“bind data-loader processes and memory to the GPU-local NUMA domain” addresses nUMA memory locality increases transfer latency and CPU-to-GPU traffic, but the current hardware or infrastructure issue is storage I/O and host page cache behavior constrain accelerator feeding. The option “profile and tune parallel dataloader processes and read-ahead for the observed access pattern” is more directly tied to the required outcome.

Useful for host software concurrency exceeds useful CPU processing capacity, but it does not remove the specific condition: storage I/O and host page cache behavior constrain accelerator feeding.

“apply the supported high-performance CPU power profile within thermal constraints” addresses host power-management policy is starving the application input pipeline, but the current hardware or infrastructure issue is storage I/O and host page cache behavior constrain accelerator feeding. The option “profile and tune parallel dataloader processes and read-ahead for the observed access pattern” is more directly tied to the required outcome.

“RDMA and collective throughput recover with lower cross-socket traffic” addresses nIC and GPU placement creates avoidable cross-socket transfers, but the current hardware or infrastructure issue is storage I/O and host page cache behavior constrain accelerator feeding. The option “input wait time declines and accepted training throughput rises” is more directly tied to the required outcome.

“context switches decline and end-to-end batch rate rises” addresses host software concurrency exceeds useful CPU processing capacity, but the current hardware or infrastructure issue is storage I/O and host page cache behavior constrain accelerator feeding. The option “input wait time declines and accepted training throughput rises” is more directly tied to the required outcome.

“chosen policy meets throughput and p99 latency targets reproducibly” addresses cPU scheduling configuration was assumed to be universally beneficial, but the current hardware or infrastructure issue is storage I/O and host page cache behavior constrain accelerator feeding. The option “input wait time declines and accepted training throughput rises” is more directly tied to the required outcome.

“tune thread count and affinity based on profiled CPU topology” addresses host software concurrency exceeds useful CPU processing capacity, but the current hardware or infrastructure issue is cPU scheduling configuration was assumed to be universally beneficial. The option “benchmark SMT and core pinning choices under representative inference traffic” is more directly tied to the required outcome.

“select and qualify CPU C-state policy with facility power constraints” addresses processor idle-state configuration conflicts with workload latency objectives, but the current hardware or infrastructure issue is cPU scheduling configuration was assumed to be universally beneficial. The option “benchmark SMT and core pinning choices under representative inference traffic” is more directly tied to the required outcome.

“choose qualified PCIe and NUMA-local NIC-to-GPU affinity” addresses nIC and GPU placement creates avoidable cross-socket transfers, but the current hardware or infrastructure issue is cPU scheduling configuration was assumed to be universally beneficial. The option “benchmark SMT and core pinning choices under representative inference traffic” is more directly tied to the required outcome.

“repeated p99 latency tests meet service objectives without instability” addresses processor idle-state configuration conflicts with workload latency objectives, but the current hardware or infrastructure issue is cPU scheduling configuration was assumed to be universally beneficial. The option “chosen policy meets throughput and p99 latency targets reproducibly” is more directly tied to the required outcome.

“RDMA and collective throughput recover with lower cross-socket traffic” addresses nIC and GPU placement creates avoidable cross-socket transfers, but the current hardware or infrastructure issue is cPU scheduling configuration was assumed to be universally beneficial. The option “chosen policy meets throughput and p99 latency targets reproducibly” is more directly tied to the required outcome.

“input wait time declines and accepted training throughput rises” addresses storage I/O and host page cache behavior constrain accelerator feeding, but the current hardware or infrastructure issue is cPU scheduling configuration was assumed to be universally beneficial. The option “chosen policy meets throughput and p99 latency targets reproducibly” is more directly tied to the required outcome.

“apply the supported high-performance CPU power profile within thermal constraints” addresses host power-management policy is starving the application input pipeline, but the current hardware or infrastructure issue is processor idle-state configuration conflicts with workload latency objectives. The option “select and qualify CPU C-state policy with facility power constraints” is more directly tied to the required outcome.

“tune thread count and affinity based on profiled CPU topology” addresses host software concurrency exceeds useful CPU processing capacity, but the current hardware or infrastructure issue is processor idle-state configuration conflicts with workload latency objectives. The option “select and qualify CPU C-state policy with facility power constraints” is more directly tied to the required outcome.

“benchmark SMT and core pinning choices under representative inference traffic” addresses cPU scheduling configuration was assumed to be universally beneficial, but the current hardware or infrastructure issue is processor idle-state configuration conflicts with workload latency objectives. The option “select and qualify CPU C-state policy with facility power constraints” is more directly tied to the required outcome.

“chosen policy meets throughput and p99 latency targets reproducibly” addresses cPU scheduling configuration was assumed to be universally beneficial, but the current hardware or infrastructure issue is processor idle-state configuration conflicts with workload latency objectives. The option “repeated p99 latency tests meet service objectives without instability” is more directly tied to the required outcome.

“profiler shows lower remote memory access and improved batch delivery” addresses nUMA memory locality increases transfer latency and CPU-to-GPU traffic, but the current hardware or infrastructure issue is processor idle-state configuration conflicts with workload latency objectives. The option “repeated p99 latency tests meet service objectives without instability” is more directly tied to the required outcome.

“packet receive rate improves and no single core saturates at peak traffic” addresses interrupt handling placement bottlenecks ingress traffic, but the current hardware or infrastructure issue is processor idle-state configuration conflicts with workload latency objectives. The option “repeated p99 latency tests meet service objectives without instability” is more directly tied to the required outcome.

Useful for NIC and GPU placement creates avoidable cross-socket transfers, but it does not remove the specific condition: host software concurrency exceeds useful CPU processing capacity.

“select and qualify CPU C-state policy with facility power constraints” addresses processor idle-state configuration conflicts with workload latency objectives, but the current hardware or infrastructure issue is host software concurrency exceeds useful CPU processing capacity. The option “tune thread count and affinity based on profiled CPU topology” is more directly tied to the required outcome.

“profile and tune parallel dataloader processes and read-ahead for the observed access pattern” addresses storage I/O and host page cache behavior constrain accelerator feeding, but the current hardware or infrastructure issue is host software concurrency exceeds useful CPU processing capacity. The option “tune thread count and affinity based on profiled CPU topology” is more directly tied to the required outcome.

“input wait time declines and accepted training throughput rises” addresses storage I/O and host page cache behavior constrain accelerator feeding, but the current hardware or infrastructure issue is host software concurrency exceeds useful CPU processing capacity. The option “context switches decline and end-to-end batch rate rises” is more directly tied to the required outcome.

“profiler shows lower remote memory access and improved batch delivery” addresses nUMA memory locality increases transfer latency and CPU-to-GPU traffic, but the current hardware or infrastructure issue is host software concurrency exceeds useful CPU processing capacity. The option “context switches decline and end-to-end batch rate rises” is more directly tied to the required outcome.

“packet receive rate improves and no single core saturates at peak traffic” addresses interrupt handling placement bottlenecks ingress traffic, but the current hardware or infrastructure issue is host software concurrency exceeds useful CPU processing capacity. The option “context switches decline and end-to-end batch rate rises” is more directly tied to the required outcome.